Researchers at the University of Cambridge have developed a new type of hafnium oxide memristor — a component that mimics synaptic connections in the brain — with switching currents roughly a million times lower than conventional oxide-based devices. The work, published in Science Advances on March 20, suggests neuromorphic hardware built with the material could reduce AI energy consumption by up to 70 per cent compared to conventional architectures.
The improvement addresses a known limitation in existing memristor technology. Conventional devices work by growing and breaking tiny conductive filaments inside an oxide layer. The process functions but introduces variability: filaments form along slightly different paths each cycle, creating noise that limits how many distinct states the device can reliably represent.
A different switching mechanism
Lead researcher Babak Bakhit, working across Cambridge’s Department of Materials Science and Metallurgy and Department of Engineering, created a hafnium-based thin film doped with strontium and titanium, grown using a two-step deposition method. Where the two material layers meet, p-n junctions — electronic gates — form naturally within the oxide. Instead of forcing a filament through the material, the device changes its resistance by adjusting the height of an energy barrier at these junctions.
The result is smooth, repeatable switching across hundreds of distinct, stable conductance levels. That granularity is a requirement for analogue in-memory computing, the architecture where data is processed in the same physical location where it is stored. Conventional computing spends a large share of its energy budget moving data between separate memory and processor units — the so-called von Neumann bottleneck. In-memory computing eliminates that transfer cost, and memristors with many stable intermediate states can serve as both the storage and the processing element simultaneously.
The Cambridge devices demonstrated reliable operation through tens of thousands of switching cycles with state retention of approximately 24 hours. They also naturally reproduce spike-timing dependent plasticity (STDP), the biological learning rule that governs how real synapses strengthen or weaken based on the relative timing of input and output signals. STDP is the mechanism that underlies Hebbian learning — the principle that neurons which fire together wire together — and reproducing it in hardware means the devices can perform certain types of unsupervised learning without external software control.
Where current neuromorphic hardware stands
The Cambridge work arrives as commercial neuromorphic processors enter production. Intel’s Loihi 3, fabricated on a 4nm process, features 8 million digital neurons and 64 billion synapses, operating at a peak load of 1.2 watts. IBM’s NorthPole architecture packs 256 million artificial synapses for image and video processing. BrainChip’s Akida 2.0 targets edge computing applications. All three platforms claim power consumption several orders of magnitude below equivalent GPU-based systems.
These chips are digital implementations — they simulate neuron-like behaviour using conventional transistor logic, optimised for low power. The Cambridge memristors represent a different approach: analogue devices where the physics of the material itself performs the computation. Analogue neuromorphic systems can in principle be more efficient than digital ones because they avoid the overhead of digitising continuous signals, but they are harder to manufacture consistently and more sensitive to material defects.
A 2025 review published in Frontiers in Neuroscience surveyed neuromorphic algorithms specifically designed for brain implants, noting that event-driven, in-memory architectures can perform neural decoding at milliwatt power levels — sufficient for implantable devices that need to operate for years without battery replacement. The review identified memristor-based crossbar arrays as a promising substrate for on-chip spike sorting and signal classification, the core tasks that an implanted BCI’s processor must perform in real time.
Why this matters for brain-computer interfaces
Current implantable BCIs rely on external or bedside processors to decode neural signals. Neuralink’s N1 chip performs some on-device processing, but the computational load for high-bandwidth decoding — translating thousands of electrode channels into motor commands or speech output — still requires substantial power. As the field pushes toward fully wireless, fully implantable systems where no external hardware is visible, the processing has to move entirely on-chip. Power consumption becomes the binding constraint: a processor that draws too much current generates heat that can damage surrounding neural tissue, and a battery that drains in hours is not viable for a clinical device.
Low-power memristors that can perform analogue computation at biological energy scales represent one path toward solving that constraint. The Cambridge devices are not ready for implantation — fabrication currently requires temperatures around 700 degrees Celsius, well above standard CMOS manufacturing limits — but they demonstrate that the underlying physics works at the power levels that on-implant processing would require.
Commercialisation path
Cambridge Enterprise, the university’s innovation arm, has filed a patent on the technology. The research was funded by the Swedish Research Council, the Royal Academy of Engineering, the Royal Society, and UK Research and Innovation. The team has identified the high fabrication temperature as the primary barrier to integration with existing semiconductor processes and is working on lower-temperature deposition methods that could make the material compatible with standard foundry workflows.
The full paper is available in Science Advances.